May the peace and blessings of the Almighty be upon you all…
1. When did PLDs come into picture and what is the reason behind that?
In early 1960s there was discrete logic. Systems were built from lots of individual chips with a spaghetti-like maze of wiring between them. It was difficult to modify such a system after you built it. After a week or two it was difficult to remember what each of the chips was for!
Manufacturing such a system took a lot of time because each design change required that the wiring be redone which usually meant building a new printed circuit board. The chipmakers solved this problem by placing an unconnected array of AND-OR gates in a single chip called a programmable logic device (PLD).
2. What is the architecture of a PLD?
The PLD contained an array of fuses that could be blown open or left closed to connect various inputs to each AND gate. You could program a PLD with a set of Boolean sum-of-product equations so it would perform the logic functions you needed in your system. Since the PLDs could be rewired internally, there was less of a need to change the printed circuit boards, which held them.
3. What is the reason behind CPLD and FPGA evolution?
Simple PLDs could only handle up to 10 –20 logic equations, so you couldn't fit an every large logic design into just one of them. You had to figure out how to break your larger designs apart and fit them into a set of PLDs. This was time-consuming and meant you had to interconnect the PLDs with wires. The wires were a big problem because eventually you would make some design change that couldn't be handled just by reprogramming the PLDs and then you would have to build a new circuit board.
The chipmakers came to the rescue again by building much larger programmable chips called complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs). With these, you could essentially get a complete system onto a single chip.
4. Briefly explain about the architecture of CPLDs and FPGAs?
A CPLD contains a bunch of PLD blocks whose inputs and outputs are connected together by a global interconnection matrix. So a CPLD has two levels of programmability: each PLD block can be programmed, and then the interconnections between the PLDs can be programmed.
An FPGA takes a different approach. It has a bunch of simple, configurable logic blocks arranged in an array with interspersed switches that can rearrange the interconnections between the logic blocks. Each logic block is individually programmed to perform a logic function (such as AND, OR, XOR, etc.) and then the switches are programmed to connect the blocks so that the complete logic functions are implemented.
5. What are the varieties of methods to make the connections between logic blocks in CPLDs and FPGAs?
CPLD and FPGA manufacturers use a variety of methods to make the connections between logic blocks.
a) Some make chips with fuses or anti-fuses that are programmed by passing a large current through them. These types of CPLDs and FPGAs are one-time programmable (OTP) because you can't rewire them internally once the fuses are blown.
b) Other manufacturers make the connections using pass transistors that are opened or closed by storing a charge on their gate electrodes using a high-voltage pulse. This type of programmable device resembles an EPROM or EEPROM: you can erase it and then place it in a special programmer socket and reprogram it. That's fine unless you have the CPLD or FPGA soldered into a circuit board.
c) Finally, some manufacturers use static RAM or Flash bits to control the pass transistors for each interconnection. By loading each bit with a 1 or a 0, you can control whether the switch is closed or opened and, therefore, whether two logic elements are connected or not. CPLDs and FPGAs built using RAM/Flash switches that can be reprogrammed without removing them from the circuit board. They are often said to be in-circuit reconfigurable or in-circuit programmable.
6. Why the chip manufacturers provide development software (like Quartus II from Altera and Project Navigator from Xilinx)?
Regardless of the interconnection method used, figuring out which switches to open and close in order to create a logic circuit would be quite a chore. That's why the chip manufacturers provide development software that takes a description of the logic design as input and then outputs a binary file, which configures the switches in a CPLD or FPGA so that it acts like the design.
Thanks and Take Care,
May the Almighty guide us in the right path always...aamin.
God Knows best...
Your Brother,
Aashiq Ahamed A
aashiq.ahamed.14@gmail.com
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