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Sunday, October 2, 2011

VLSI - Q & A...




Assalaamu Alaikum,

May peace and blessings of ALLAH (swt) be upon you and your family...aameen

Here are some of the VLSI related questions and answers which may be helpful to you. If you find this useful, please share it with your friends...

  1. What do you mean by Front End design and Back End design?
Front End design means Verification of a design whereas Backend Design means Analysis of a Design. In the VLSI design steps Writing HDL codes/Schematic, Simulation and Compilation belong to Front end design. And Synthesis, Floorplanning, Placing and Routing belong to Back end Design.

  1. Mention some Front end design tools?
               ModelSim from Mentor Graphics is the best Example. In this tool we can write and Simulate our design and can’t do anything apart from that. Active HDL from Aldec is an another example.

  1. Mention some Back end design tools?
RailMill, Dracula, Assura, Herculas etc…

  1. Why should I perform Synthesis?
 Synthesis is the process which will convert our HDL into gate level Netlist (or we can say, HDL to graphical representation of our design). This netlist is used for other VLSI design steps such as Placing and Routing.

  1. If I say a particular code is NON-SYNTHESIZABLE, what do I mean?
It means that the particular code can not produce suitable logic circuit/element to proceed further in the design process.

  1. Mention Some Synthesis tools?
XST (from Xilinx), Leonardo Spectrum (from Mentor), Synplify Pro (from Synplicity), Design Compiler ( from Synopsys) etc…

  1. Have you heard about RTL style of coding, if yes what is it?
Yes. If I say a particular code is following RTL style then it means that the particular code is Synthesizable.

  1. What are entity and Architecture in VHDL?
Entity describes about the external view of a project whereas Architecture explains about the internal view of a project

  1. If Quartus II related to Altera then ISPLever related to?
Lattice Semiconductor Corporation.

  1. What is the difference between a Signal and a Variable in VHDL?
During synthesis a signal can be represented as Register and a Variable can be represented as Wire.

  1. What is the real purpose of using Stick and Layout diagrams?
Without them you can not Produce your chips. The popular formats which goes to the Foundry like GDSII and CIF based on layout diagrams.

  1. If Vera related to VCS then E related to?
Specman Elite. Vera and E are nothing but the verification languages and, VCS and Specman Elite are their corresponding Compilers

  1. How does a PLD (SPLD/FPGA/CPLD) understands your higher level programming i.e. HDLs?
Through the bitstreams produced after performing VLSI design steps.

  1. In VLSI design steps, what do you mean by “Programming”?
Progamming means Downloading to the hardware.

  1. Mention some ASIC design tools?
There are lots of them. Please visit the websites of Commercial EDA tool suppliers like Synopsys, Cadence and Magma to learn better.

  1. I can design a CPLD or an FPGA using tools from Cadence or Synopsys. True or False?
Using the tools from Cadence or Synopsys you can design whatever Chips you want. If I say that then it includes CPLDs and FPGAs also. Hence the answer is true.

  1. In the name FPGA what does FIELD PROGRAMMABLE mean?
You can explain this in two ways.

v     In electronics Field means Voltage, that is why we call FET as field effect transistor. Similarly in FPGA, it explains that Gate of Arrays which are programmable if I supply a Voltage.

v     Gate of Arrays which are programmable by the user itself instead of the manufacturer.

  1. Explain about Sensitivity List in HDLs?
Sensitivity list is the list which you notice next to PROCESS or 
ALWAYS statements in VHDL and Verilog HDL respectively. It contains the list of variables that will change the output of a project.

For example, let us assume that we are implementing an OR gate project. For this project we have two inputs (a and b) and one output (c). We know that, the output c changes only when the inputs (a and b) change. Hence the variables a and b should be placed inside the sensitivity list.

To put it in a simple way, those variables which changes the output of a project should be placed inside the sensitivity list.

  1. Why FPGAs does not come under the category of PLDs?
Because FPGAs have a different architecture when compared to their counterparts, the PLDs.

  1. What is the difference between a PAL and PLA?
In PLAs, both the input and output planes are programmable whereas in PALs only the input plane is programmable and the output plane is fixed.

  1. Why should one use Software tools such as Project Navigator or Quartus II?
Programmable devices (PLDs and FPGAs) contains switches which needs to be programmed (neither High or Low) to get our designs. Manually programming the switches is very difficult, infact nearly impossible. That is why we use software tools such as Project Navigator or Quartus II or any other similar tools. These tools produce programming files or binary files after performing VLSI design steps which are used to program the switches in the programmable devices.

  1. Complex designs should be programmed using Structural way of Modeling. Am I correct?
To a certain extent, yes. But not always, it depends on the circumstances
and designer’s abilities. For instance, let us assume that we are trying to implement a fulladder design.

One way of designing is, we know that fulladder design contains two ‘halfadders’ and one ‘or’ gate. Now you write a program for halfadder and call the corresponding entity two times in the main project and write a program for ‘or’ gate and call it once in the main program. The end result, within three steps inside the architecture we finish the project.

The other way is, what will happen if the designer doesn’t able to visualize fulladder into two ‘halfadders’ and one ‘or’ gate. On that case, he designs the full adder circuit with two ‘xor’ gates and two ‘and’ gates and one ‘or’ gate (or in any other way). To do this in structural way, he writes the program for ‘xor’ gate, ‘and’ gate, ‘or’gate and calls these programs in the main project. The end result, it takes five steps inside the architecture to finish the project. If he designs the same project in data flow method, he still needs to write five steps to finish the project and addition to that we has saved some time in writing programs for ‘xor’,’and’ and ‘or’.

Hence if the designer has the expertise to visualize a complex circuit as blocks (like halfadders in fulladder circuit) then structural way of programming will be of immense use. Or else it is better to hold on with Data flow way of modeling.

  1. What do you mean by Prototyping?
Usually when an ASIC designer wants to implement his design, he will try it out on a similar hardware first and then goes for Actual Manufacturing. This kind of duplication is known as Prototyping. Prototyping is Very important to every ASIC design engineer. 


2 comments:

'ஒருவனின்' அடிமை said...

weldon brother

ராஜகிரி ஹாஜா மைதீன் (அபு நிஹான்) said...

மாஷா அல்லாஹ். எவ்வளவு பெரிய வேலையை சத்தமில்லாமல் செய்து கொண்டிருக்கிறீர்கள் சகோ.

வாழ்த்துக்கள். அல்லாஹ் உங்களுக்கு அருள் பாலிப்பானாக

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