Sunday, July 26, 2015

Hardware Verification Languages - Heard about them?

May peace and blessings of the Almighty be upon you and all...

You may quite often heard about SPECMAN, E and VERA in the IC design world.

  • What are those?
  • Where they are used?
  • Why they are used? and
  • What is their background?

This article will try to answer the above questions in the simplest way possible.

Let's start...

In normal practice we write a HDL code for our design and use Test Benches (written in HDLs) to verify our designs. We have gate count increasing every day, thus the challenge to verify them. In the past the verification was done with languages which were meant for designing..

In those situations you need something unique to verify your designs at faster rate possible.

Writing test benches with HDLs which are primarily meant for designing will not help in verifying your circuits with higher gate density…

That’s why in today’s ASIC world they use different languages to verify your designs. Those are called HARDWARE VERIFICATION LANGUAGES (HVLs).

If HDLs meant for designing, then HVLs meant to verify those HDL codes.

If VHDL and Verilog HDL are the HDLs we know, then the famous HVLs used in today’s world are E and VERA.   

E and VERA are used basically to describe testbenches, which has the capability to generate random test vectors, ability to interface with HDL's, provides means to do functional coverage.

Hence design people working in ASIC field used to design their circuits using HDLs and verify their designs using HVLs.( In educational institutions, people used to design and verify their circuits using the same languages i.e. HDLs).

Hope by this time you may understood the difference between the HDL and HVL.

Then what is SPECMAN?

          Specman is basically the tool/compiler/debugger to work with E language.

Then how can I compile my testbench which is written in VERA language?

        To Compile/debug your testbenches written in Vera language we have a tool by name VCS Compiler.

Now you may have one question…

What is the difference between E and VERA Languages when they perform the same task i.e Verifying our design?

The answer is quite simple... E language is from CADENCE and VERA is from Synopsys and both the languages have the syntax on their own.

How much easy is to learn HVLs?

Learning E or Vera is quite a simple task if you are aware about C++ language. They resemble C++ and you can learn within a month period.

Let us meet in a another blog post, God Willing..

Your brother,
Aashiq Ahamed A

Monday, June 9, 2014

Beware of fake interview calls...

May peace and blessings of the Almighty be upon you all...

Recently, one of my students, forwarded a interview call letter and requested me to authenticate the genuineness of it. The crux of the matter is that, it was from industry giant Robert Bosch limited and it asked the candidates to deposit Rs.9400 as security deposit which will be refunded after the interview. 

On the first look, it appeared so genuine as it got email id in the name of bosch ( and contained the postal address of Bangalore Bosch ltd. Even it had "confidential" prints on it and also it said "we don't use email ids apart from bosch ids" etc etc. Have a look at the interview call letter below. 

Fig 1

Fig 2

But, on a very careful examination,  one can find this as fake, 
  • as the email id from which this mail was sent does not belong to HR department of Bosch. 
  • The undersigned is not the employee of Bosch ltd. 

I request all those who are reading this to be aware of these fraud as they look so original. Regarding this a complaint was raised in cyber crime. Fine, how could one find these are genuine? 

  • First, understand that, no genuine company calling for interviews within India will ask for security deposit even before the interview. 
  • If you receive such bogus mails, search the company name, go to the company website and make sure the email ids of the HR department are matching. 
  • Get the telephone numbers from the company website. Try directly calling to the HR department of the company and enquire about the email. Do not ever make a call to the numbers mentioned on the fake interview letter.

As I said above, utmost awareness is required in this regard, otherwise people will fall pray to this. Hence I request those who are reading this to create awareness amongst others. Sharing this article may help many more people. 

Thanks and Let us meet in an another blog post (God willing)

Your brother,
Aashiq Ahamed A

Tuesday, June 3, 2014

Speed Grade

May peace and blessings of the Almighty be upon you all...

Many of us come across SPEED GRADEs in SPLDs and CPLDs. Let us see how to define them.

For example, let us take a CPLD from Altera., EPM3128ATC144-10

Here the last two letters “10” is nothing but the SPEED GRADE. Usually speed grades are mentioned in “nano seconds”. Here it is 10 ns.

Defining Speed Grade:

We know that a typical CPLD contains two or more PAL-like Blocks (also called as Logic Array Block (LAB)). Each LAB contains a bunch of Macrocells. 

SPEED GRADE represents the propagation delay from an input pin on the MACROCELL to an output pin, assuming that the flip flop in the macrocell is bypassed. (This is because flip flops store the value at a particular point in time indefinitely).

To be more precise, let us see an example. Let us assume that we are implementing a AND gate (with inputs a and b, and output c) in the CPLD, EPM3128ATC144-10.

We should understand that, from the input a to the output c, the propagation delay is 10ns as per the selected CPLD. Similarly from the input b to output c the propagation delay is 10ns. See the above fig (taken from ALTERA Quartus II) to understand better.

Let us see another CPLD from XILINX, XCR3128TQ144 – 5,

This tells that the propagation delay is 5ns from the input pin on the macrocell to the output pin (i.e. from a to c and b to c). 

Hence, SPEED GRADE represents the propagation delay from an input pin on the MACROCELL to an output pin.

God willing, let us meet in an another blog post. 

Your brother,
Aashiq Ahamed A

Friday, July 12, 2013

The Chips are up...

May the peace and blessings of the Almighty be upon us...

Few years back, Mr. Jhinuk Chowdhury of TIMES GROUP wrote a very insightful article named “THE CHIPS ARE UP”. This piece analyses the future opportunities in the field of Semiconductor/VLSI and the challenges faced by Electronics/Electrical engineers. I give the entire article below and hope this will be of immense use. 

The semiconductor industry is set to add around 3.5 million heads by 2015 to its existing count of 20,000. Jhinuk Chowdhury learns more about the opportunities that this industry offers

    Just being an electronic engineer doesn’t qualify you to get a job in the semiconductor industry. You need to have a hunger to learn. A burning desire to know how things work and a background of dismantling electronic toys to understand how they function, would also go a long way. If the above mentioned is an extension of your profile, then the semiconductor industry is looking for you. Companies like Freescale, Texas Instruments, KPIT Cummins, Cadence, STMicroelectronics and many more are recruiting electronic engineers with excellent analytical aptitude and quick learning abilities at salary packages higher than those offered by the IT industry. One small deterrent here is that academia provides for only 20 per cent of the required manpower. To give you an industry example, while KPIT Cummins needs 150-200 people every year, it only manages to find 80 relevant candidates. So, while the talent crunch is evident, the industry looks more promising than ever. Let’s find out why one should should opt for this industry and who gets in. 


Job creation in this sector would be in the areas of Integrated Circuit (IC) Design, VLSI, EDA (electronic design automation), manufacturing operations related to testing, packaging, logistics etc. 

    The industry is hiring Electronics/Electrical engineering professionals with knowledge of digital design, simulation, synthesis tools, computer architecture, and mixed signal design, and strong mathematical aptitude. Also, a fair knowledge of different sectors, like consumer electronics, mobile devices, home security systems, auto components etc. are absolutely essential. This however does not undermine the need for behavioural skills. As for Philips Electronics India Ltd, while technical competencies are a must, behavioural aspects are just as important. Says Rajeev Mehtani, VP & Site Innovation Manager, Philips Semiconductors, “We look for a mindset committed to quality, and a ‘not giving up’ attitude with global perspective.” The Philips Innovation Campus at Bangalore, has, as of now, been awarded 16 patents. 


    As mentioned above, one of the factors that would draw most candidates towards this industry is the generous compensation offered. Poonam Shenoy, ISA agrees that the salaries offered in this industry are much higher than any other technology industry, “It starts from Rs 4.5 lakhs which is significantly higher to what is offered by the software industry.” Veena Kumar, HR Manager, Open Silicon, even feels that it might go upto Rs 6.5 lakh for a fresh graduate who displays the right aptitude and is a logical fit. 

    In terms of vertical growth, one can start as a research and design engineer and move up to a project leader, a senior design engineer, or systems architect. 


Says B S Murphy, CEO, Human Capital, “We have always underplayed our Math strength, whereas the industry needs super math and algorithm skills.” Another key issue is the lack of training facilities. Praveen Acharya, VP-ATS, Semiconductor Group KPIT, feels that academia has, so far, given almost a ‘stepmotherly’ treatment to the semiconductor industry. Girish Wardadkar, President & ED, KPIT, feels India is no match to the semiconductor manufacturing activities happening in China, “China is definitely more appealing to chip manufacturing firms in the US and UK, which explains why India, today, may have an edge in design services but not manufacturing.” 

    An ecosystem needs to be created where the industry and academia join hands to identify the global needs of the industry and churn out relevant engineers. Exclusive design schools validated by the industry and sponsorship of laboratories could definitely accelerate the process of further developing this industry"

Please Note:
The above picture is not from the Times of India article.

Let us meet in a another blog post (God Willing).

Your brother,
Aashiq Ahamed A

Monday, July 1, 2013

SMVEC workshop pics...

May peace and blessings of the Almighty be upon us all..

The company I belong to, Bistate Systems, conducted five days onsite training program (or workshop) in VLSI DESIGN, recently, at one of the popular educational organizations of Pondicherry, Sri Manakula Vinayagar Engineering College (SMVEC). This workshop, in which, I trained the students of Instrumentation & Control Engineering (Third year) on the basics of VLSI Design, is a part of Industry-Institute interaction on knowledge sharing. 

Response from the students was very encouraging and positive (All praise to the Almighty). I thank the management, teaching staff & the assisting staff for the excellent hospitality provided. The workshop went like this, technical sessions with practical knowledge along with competitive assessments. Certificates were provided on the basis of ranks secured at the competition. Here are some of the pics of the moment...

God Willing, we will meet in a another blog post.

Your brother,
Aashiq Ahamed A