May peace and blessings of the Almighty be upon you all...
Many of us come across SPEED GRADEs in SPLDs and CPLDs. Let us see how to define them.
For example, let us take a CPLD from Altera., EPM3128ATC144-10
Here the last two letters “10” is nothing but the SPEED GRADE. Usually speed grades are mentioned in “nano seconds”. Here it is 10 ns.
Defining Speed Grade:
We know that a typical CPLD contains two or more PAL-like Blocks (also called as Logic Array Block (LAB)). Each LAB contains a bunch of Macrocells.
SPEED GRADE represents the propagation delay from an input pin on the MACROCELL to an output pin, assuming that the flip flop in the macrocell is bypassed. (This is because flip flops store the value at a particular point in time indefinitely).
To be more precise, let us see an example. Let us assume that we are implementing a AND gate (with inputs a and b, and output c) in the CPLD, EPM3128ATC144-10.
We should understand that, from the input a to the output c, the propagation delay is 10ns as per the selected CPLD. Similarly from the input b to output c the propagation delay is 10ns. See the above fig (taken from ALTERA Quartus II) to understand better.
Let us see another CPLD from XILINX, XCR3128TQ144 – 5,
This tells that the propagation delay is 5ns from the input pin on the macrocell to the output pin (i.e. from a to c and b to c).
Hence, SPEED GRADE represents the propagation delay from an input pin on the MACROCELL to an output pin.
God willing, let us meet in an another blog post.
Aashiq Ahamed A