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Sunday, July 26, 2015

Hardware Verification Languages - Heard about them?




May peace and blessings of the Almighty be upon you and all...

You may quite often heard about SPECMAN, E and VERA in the IC design world.

  • What are those?
  • Where they are used?
  • Why they are used? and
  • What is their background?

This article will try to answer the above questions in the simplest way possible.

Let's start...

In normal practice we write a HDL code for our design and use Test Benches (written in HDLs) to verify our designs. We have gate count increasing every day, thus the challenge to verify them. In the past the verification was done with languages which were meant for designing..

In those situations you need something unique to verify your designs at faster rate possible.

Writing test benches with HDLs which are primarily meant for designing will not help in verifying your circuits with higher gate density…

That’s why in today’s ASIC world they use different languages to verify your designs. Those are called HARDWARE VERIFICATION LANGUAGES (HVLs).

If HDLs meant for designing, then HVLs meant to verify those HDL codes.

If VHDL and Verilog HDL are the HDLs we know, then the famous HVLs used in today’s world are E and VERA.   

E and VERA are used basically to describe testbenches, which has the capability to generate random test vectors, ability to interface with HDL's, provides means to do functional coverage.

Hence design people working in ASIC field used to design their circuits using HDLs and verify their designs using HVLs.( In educational institutions, people used to design and verify their circuits using the same languages i.e. HDLs).

Hope by this time you may understood the difference between the HDL and HVL.

Then what is SPECMAN?

          Specman is basically the tool/compiler/debugger to work with E language.

Then how can I compile my testbench which is written in VERA language?

        To Compile/debug your testbenches written in Vera language we have a tool by name VCS Compiler.

Now you may have one question…

What is the difference between E and VERA Languages when they perform the same task i.e Verifying our design?

The answer is quite simple... E language is from CADENCE and VERA is from Synopsys and both the languages have the syntax on their own.

How much easy is to learn HVLs?

Learning E or Vera is quite a simple task if you are aware about C++ language. They resemble C++ and you can learn within a month period.

Let us meet in a another blog post, God Willing..

Your brother,
Aashiq Ahamed A